1. Field of the Invention
The present invention relates to a manufacturing method for a strained silicon wafer in which a SiGe layer and a strained Si layer are deposited on a silicon substrate.
2. Description of the Related Art
In these years, a strained silicon wafer in which a SiGe layer is epitaxially grown on a single crystal silicon substrate and a strained Si layer is epitaxially grown on the SiGe layer has been proposed. By using the strained Si layer as a channel area, the strained silicon wafer enables the carrier movement at double or more the speed as fast as using the normal bulk Si wafer.
Therefore, it has been noted that the strained silicon wafer is suitable for the fast MOSFET, MODFET, HEMT and the like.
In the strained silicon wafer having the above described SiGe layer, when the strained Si layer used as the channel area is epitaxially grown, it is required to grow the SiGe layer on the silicon substrate for serving as base material of the epitaxial growth of the strained Si layer.
However, due to a difference in a lattice constant between Si and SiGe, a misfit dislocation occurs when the SiGe layer is epitaxially grown on the silicon substrate. And a threading dislocation caused by the misfit dislocation reaches a surface of the silicon substrate at high density. The same dislocation continuously exists at high density up to the strained Si layer formed on the SiGe layer.
The dislocation in the strained Si layer causes a junction leakage current to be greatly increased when forming the device elements.
Moreover, there is a problem that due to threading dislocations and residual strain energy, an irregularity undulation so called a crosshatch occurs on the surface of the strained Si layer. Therefore, conventionally, various proposals have been made to reduce the threading dislocation density.
For example, in the Japanese Patent Examined Publication No. JP-B-2792785, a method for manufacturing a semiconductor device was disclosed in which a graded SiGe layer having the Ge component increased at a concentration gradient of about 25%/μm or less is epitaxially grown on the single crystal silicon substrate at 850° C. or higher, and then the strained Si layer is epitaxially grown on the graded SiGe layer, a thickness of the strained Si layer being desirably in a range from 100 to 1000 Å.
Also, in Japanese Patent Unexamined Publication No. JP-A-2002-118254, a semiconductor wafer was described in which a step graded SiGe layer of SiGe layer having the Ge composition ratio progressively increased is formed on the silicon substrate. A relaxed SiGe constant composition layer and a strained Si layer having the constant Ge composition ratio are provided on the step graded SiGe layer. The threading dislocation density can be reduced by increasing the number of steps. Then, it is shown that the film thickness of the step graded SiGe layer is 1.5 μm, the film thickness of the relaxed SiGe constant composition layer is ranging from 0.7 to 0.8 μm, and the film thickness of the strained Si layer is ranging from 15 to 22 nm.
Also, in Japanese Patent Unexamined Publication No. JP-A-2003-229360, a semiconductor substrate manufacturing method has been described. That is, after an SiGe layer having a Ge concentration of 22 atomic % or more is deposited on a silicon substrate until the thickness of the SiGe layer becomes about 100 to 500 nm, H+ ions are injected into the SiGe layer, the silicon substrate and the SiGe layer are thermally annealed so as to relax the SiGe layer, and the strained Si layer is deposited on the relaxation SiGe layer until the thickness of the strained Si layer becomes about 5 to 30 nm thick.
Also, in Japanese Patent Unexamined Publication No. JP-A-2003-197544, a semiconductor substrate was disclosed in which the SiGe layer has a film thickness thinner than double of a critical film thickness. The critical film thickness is to cause a lattice relaxation by occurring dislocation due to increased film thickness. The second SiGe layer consists of an SiGe graded SiGe layer having the Ge composition ratio progressively increased toward the surface and an SiGe constant composition layer disposed on the graded SiGe layer with a Ge composition ratio on an upper face of the graded SiGe layer that are deposited alternately and with continuous Ge composition ratio in a state where a plurality of layer are deposited. The Ge composition ratio on a lower face of the second SiGe layer is lower than the maximal value in a layer of Ge composition ratio on the first SiGe layer. Whereby the given thickness of the strained Si layer is formed 20 nm, for example.
However, in the Japanese Patent Examined Publication, the threading dislocation density is in an order of 105 cm−2 in an example, and it is not suggested that the thickness of the strained Si layer has any influence in respect to the lower dislocation density.
Similarly, for the semiconductor substrate as disclosed in the Japanese Patent Unexamined Publications Nos. JP-A-2002-118254 and JP-A-2003-229360, the method for relaxing the SiGe layer to reduce the dislocation density was only disclosed, but the relationship between the thickness of the strained Si layer and the reduction in the threading dislocation density was not described.
Moreover, for the semiconductor substrate as disclosed in the Japanese Patent Unexamined Publication No. JP-A-2003-197544, the thickness of the strained Si layer was formed 20 nm as an illustration, but there was no description that its thickness had any influence on reduction in the threading dislocation density.
Thus, as a result of investigations taking notice of the relationship between the strained Si layer and the reduction in the threading dislocation density, the present inventor has found that the dislocation density is reduced in the predetermined thickness of the strained Si layer.